1. Field of the Invention
The present invention relates to a buffer using a dynamic threshold-voltage MOS transistor to improve operating speed of an MOS transistor.
2. Background of the Invention
A dynamic threshold-voltage MOS (DTMOS) transistor is a device that improves the structure of an MOS transistor to obtain high-speed performance. A characteristic of this transistor is that an input signal to the gate is applied also to the body in the SOI structure (or the back-gate in the bulk structure). FIGS. 8 and 9 show the structures of an NMOS transistor and a PMOS transistor, respectively, both having the SOI structure. In FIG. 8, the body is a P.sup.- region, while an N.sup.- region in FIG. 9. We will give the following description, laying stress on the SOI structure. FIG. 12 shows the relation between a body potential and a threshold voltage of the NMOS transistor, and FIG. 13 shows like relation of the PMOS transistor. The relations are common both in the SOI and the bulk structures. The relation between the body potential and the threshold voltage in the SOI structure has been introduced, for example, by Jeane Pierre Colinge, "Silicon on Insulator Technology Material to VLSI," Kluwer Academic Publishers, 1991, p. 118, while the relation in the bulk structure has been introduced, for example, by H. Yanai and M. Nagata, "Integrated Electronics (1)," CORONA PUBLISHING CO., LTD., 1987, p. 69. In the NMOS transistor, as the applied voltage to the body is increased in the positive direction, the threshold voltage is reduced to zero. In the PMOS transistor, on the contrary, as the applied voltage to the body is increased in the negative direction, the threshold voltage is increased in the positive direction to zero.
As an example of using such a DTMOS transistor, a CMOS buffer is shown in FIG. 10. First, considering the operation of an NMOS transistor N1 in FIG. 10, when the input signal makes a transition from low to high, the body potential also makes a transition from low to high, and the threshold voltage of the NMOS transistor N1 approaches zero as shown in the graph of FIG. 12. This increases speed in turning on the NMOS transistor N1, thereby improving discharge capability of the CMOS buffer. Next, as for the operation of a PMOS transistor P1 in FIG. 10, when the input signal makes a transition from high to low, the body potential also makes a transition from high to low, and the threshold voltage of the PMOS transistor P1 approaches zero as shown in the graph of FIG. 13. This increases speed in turning on the PMOS transistor P1, thereby improving charging capability of the CMOS buffer.
In the DTMOS transistor, however, the trade-off for high-speed performance is increased power consumption. For example, in the NMOS transistor, since the body potential is high when the input signal is high, the body P.sup.- and the source N.sup.+ form a forward-bias pn junction. As is well-known, the voltage-current characteristics of the pn junction is as shown in FIG. 11, where I.sub.pn is current flowing from body to source of the NMOS transistor and V.sub.BN is the body potential, and the rising voltage is approximately 0.6 V. Since a high-level signal is generally not less than 0.6V, current will continuously flow from body to source during the high state of the input signal, which increase power consumption. This goes for the PMOS transistor. That is, since the source P.sup.+ and the body N.sup.- of high potential form a forward-bias pn junction when the input signal is low, current will continuously flow from source via body to the input during the low state of the input signal.
Thus, an object of the present invention is to reduce a constant flow of current to the body while keeping high-speed performance in the DTMOS transistor. For the NMOS transistor, this can be accomplished by increasing the applied voltage to the body to reduce the threshold value only when the signal makes a transition, while after the completion of the transition, reducing the applied voltage to increase the threshold value. That goes for the PMOS transistor except that the direction of the voltage is reversed.
Although not having such an object, some prior arts may have a potential of giving an effect on the aforementioned issues. One example is the technique disclosed in Japanese Patent Laid-Open No. 9-83338, for suppressing fluctuations of ground potential due to discharge current occurring when the NMOS transistor is turned on, in the buffer circuit of the CMOS structure. According to this technique, the NMOS transistor is connected at its output end to the source of another PMOS transistor not in the CMOS structure, and the PMOS transistor is connected at its drain to the body of the NMOS transistor (connected always to a constant voltage source) and receives pulses at its gate only when the input signal to the gate of the CMOS buffer makes a transition. Such a structure prevents fluctuations of the ground potential, because within a short initial period when the input signal starts a transition, the PMOS transistor is turned on to apply current to the body of the NMOS transistor in the CMOS structure, while at other times, the current flowing in the NMOS transistor is prevented. In this structure, it is possible to temporarily increase the body potential of the NMOS transistor when the input signal makes a transition from low to high, depending on other settings for a voltage source connected constantly to the body, and so on. Thus, the effect of the present invention may be obtained.
Another example is the technique for improving operating speed, disclosed in T. W. Houston, "A Novel Dynamic Vt Circuit Configuration," Proceedings 1997 IEEE International SOI Conference, Oct. 1997, pp.154-155. As in Japanese Patent Laid-Open No. 9-83338, according to this technique, the NMOS transistor is connected at its output end to the source of another PMOS transistor out of the CMOS structure, and the PMOS transistor is connected at its drain to the body of the NMOS transistor. The PMOS transistor, however, receives at its gate an input signal to an ante-stage inverter of the CMOS buffer. In such a structure, the PMOS transistor is turned on before the input signal to the CMOS buffer makes a transition from low to high, so that the high-level output of the CMOS buffer is propagated to the body of the NMOS transistor, reducing the threshold value. This shortens the transition time, thereby achieving high-speed performance. The output of the CMOS buffer remains low until the next transition, so that the PMOS transistor not in the CMOS structure is maintained in the on state. This keeps the body potential of the NMOS transistor low, preventing the current flow from the body to the source, to thereby suppress power consumption. As is the case with the NMOS transistor, the PMOS transistor in the CMOS structure is, in a similar fashion, connected to another NMOS transistor not in the CMOS structure. Thus, the same as described above can be said of the PMOS transistor.
The former example, however, has an disadvantage of increasing a circuit scale, because an inverter and an AND circuit are required to produce pulses at the transition of the input signal.
The latter example also has an disadvantage. When the input signal to the CMOS buffer makes a transition from low to high later on, the body potential of the NMOS transistor in the CMOS buffer floats since the PMOS transistor out of the CMOS structure is off. The floating potential increased by noise makes the threshold voltage reduced. This may turn on the NMOS transistor which has to be turned off, and thereby the circuit ends up in error. The same can be said of the PMOS transistor.